STELLARSILICON

Faster, energy-efficient AI chips from edge to orbit.

One in-memory architecture for robots, drones, satellites and orbital data centers. Supported models run without retraining.

  • Up to80×less energy than Jetson
  • Up to49×more tokens/s than Jetson
  • TodayLiveon our FPGA prototype
Try it live Evaluate your workload

01The constraint

AI has outgrown the power budget

Robots, drones and satellites have fixed power and little cooling. Data-center chips assume plenty of both.

The four limits on AI at the edge A drone above the ground. It runs on a fixed battery while one high-end GPU alone wants 700 W. It is sealed, with little room to cool a chip. Every extra watt adds hardware, size and cost. Its link to the ground is slow and patchy, so it has to decide on board. Power fixed battery or panel one GPU alone: 700 W Size + cost more watts, more hardware bigger, costlier system Heat sealed, no airflow little room to cool Latency slow, patchy link so decide on board
  • Power

    Batteries and solar panels set a hard limit. One high-end GPU wants more than a small satellite supplies.

  • Heat

    Sealed devices have no fans. In orbit, heat leaves only through radiators.

  • Size and cost

    Every extra watt means a bigger battery, solar array or radiator.

  • Latency

    Cloud links are slow and patchy, so the answer must be computed on board.

02The architecture

We compute where the weights live

Conventional chips spend more energy moving weights than doing the math.

Stellar computes inside the memory, cutting data movement, energy and latency.

Supported models run without retraining.

In-memory computing compared with a conventional processor A conventional processor keeps memory and compute apart, so every weight is carried between them and that movement costs more energy than the arithmetic. Stellar computes inside the memory array: inputs enter, the weights stay where they are, and results come out. CONVENTIONAL PROCESSOR MEMORY COMPUTE Weights are carried to the compute units. This data movement dominates energy use. STELLAR · COMPUTE IN MEMORY INPUTS wwww wwww wwww wwww WEIGHTS STAY PUT RESULTS The computation happens inside the memory. Less data movement, less energy, lower latency.

03Stellar Edge

Up to 80× less energy than NVIDIA Jetson

One Stellar Edge Performance chip, for edge devices and satellites.

Up to80×less energy per token
Up to49×more tokens per second
Up to51×lower cost per token

Against NVIDIA Jetson Orin Nano Super, measured: Gemma 3 270M, 8 users. Stellar: pre-silicon design targets.

Energy × time on ResNet-50

BenchmarkResNet-50 v1.5, MLPerf model
ScenarioContinuous stream; NVIDIA and SiMa.ai batched
EnergyPower ÷ images per second
Accuracy99.2 % of full precision (target 99 %)

Follows the MLPerf method.

04Edge to orbit

One architecture, from Earth to orbit

Edge devices, satellites and orbital data centers need the same thing: low-latency inference on tight power. The same core architecture with radiation-aware design serves all three.

One architecture from the edge to orbit A dotted path rises from a robot and a drone on the ground, through a small satellite, to an orbital data center. The same Stellar chip sits at every stop. Edge Robots, drones, cameras Satellites Smaller, cheaper, smarter Orbital data centers Less solar and radiator hardware
  • Edge and on-prem

    More inference in the same power and thermal budget.

  • Satellites

    More onboard processing, less downlink, and a smaller, cheaper satellite.

  • Orbital data centers

    Solar arrays and radiators scale with every watt. Lower power means less of both.

Up to 24× less energy than NVIDIA H100

Stellar Edge Performance: 10 chips on one card, 80 GB of LPDDR5X, no HBM. Two of its chips match an NVIDIA H100 serving 16 users on Gemma 3 1B, at 12 W instead of 253 W.

24×less energy per token than an H100
26×less energy per image than an H100
80 GBmemory at 2.7 TB/s, no HBM
NVIDIA H100253 W
Small satellite bus~100 W
Stellar Edge Performance~12 W

Gemma 3 1B, 16 users, 128 + 64 tokens per request, prompt included: H100 SXM measured with vLLM, GPU power. ResNet-50, both batched: H100 from MLPerf Inference v4.0. Stellar: pre-silicon design target, chip and memory power.

05Where we are

From FPGA to custom silicon

  1. Published

    Peer-reviewed chip designs

    Two chip designs published through peer review.

  2. Today

    Running on FPGA

    Language, vision and control models run live on our FPGA prototype.

  3. Next

    Scale up

    Grow the core to support larger models and heavier workloads.

  4. Then

    Custom silicon

    Tape out our first chip, for edge and space.

06Live on Stellar

Real models, running on our FPGA prototype

Our FPGA prototype is wired to this site. Every answer shows whether it came from the board or hardware emulation.

Live Inference

Doom, a lunar lander, handwriting and sketches, plus a fruit-fly brain in 4-bit arithmetic.

Run live inference →

LLM on Chip

Chat with Gemma 3 270M on our FPGA prototype.

Ask the model →

Testbed

Build a board from Stellar Edge-2 chips and compare it with measured NVIDIA, Hailo and Axelera results.

Open the explorer →