STELLAR SILICON

AI inference in orbit,
where compute keeps scaling.

Earth's power infrastructure is becoming a constraint on the growth of AI. Space offers abundant solar energy, but conventional data-center hardware is poorly suited to orbit: a high-end GPU can consume around 700 watts, while a small satellite bus may supply closer to 150.

Stellar Silicon approaches the problem at the chip level. Our architecture performs computation directly where the model weights are stored, reducing the energy normally spent moving data between memory and processing units. More inference per watt means more useful compute within a satellite's tight power and thermal envelope.

  • —projected less energy per inference than an H100, at matched 8-bit precision
  • —projected lower batch-1 latency than an H100
  • —to do an H100's work, inside a satellite's ~150 W budget

We have already published two peer-reviewed chip designs. The demo below is not a software simulation: it runs a real 256→64→32→10 neural network on an FPGA prototype connected directly to this website.

The core architecture is working today on FPGA. We will first scale it to support larger models and higher workloads, and then transition from this validated prototype toward custom silicon designed for orbital AI inference.

OPEN DIGIT LAB ↓
In-memory computing compared with a conventional processor A conventional processor keeps memory and compute apart, so every weight is carried between them and that movement costs more energy than the arithmetic. Stellar-1 computes inside the memory array. Each activation drives one row and is shared along every cell in that row; a weight sits at each row-column crossing. The products accumulate as propagation delay down each column, and each column has its own time-to-digital converter that reads the arrival time as that output's result. CONVENTIONAL PROCESSOR MEMORY COMPUTE weights are carried to the compute units this data movement dominates energy use STELLAR-1 · TIME-DOMAIN IN-MEMORY ONE ACTIVATION PER ROW, SHARED ALONG IT wwww wwww wwww wwww WEIGHTS STAY PUT TDCTDCTDCTDC ONE OUTPUT PER COLUMN products accumulate as delay down each column no separate adder, no data movement, no ADC

INTERACTIVE DEMONSTRATION

Digit inference lab

Use a centered, single-stroke handwritten digit for the closest MNIST-style input.

The FPGA is in Bangalore, India. It is online 10:30 AM – 12:30 PM PT (11:00 PM – 1:00 AM IST). In that window your digit runs on the real board. Outside it, a hardware-emulated software model answers instead — the board's exact weights and quantisation, run in software — and the result says so.

INPUT BUFFER

Draw one digit

CENTERED
16 × 16
Y / 00X / 15DRAW ONE DIGIT